This invention relates generally to synchronizing (sync) signal separating circuits and specifically to such circuits that are adapted to process sync signals of differing characteristics such as those associated with NTSC signals, HDTV signals and various computer signals.
The rapid proliferation of video signals other than in the NTSC television format has highlighted a need for sync signal separating circuits that are capable of accommodating such signals that have differing characteristics. In general, digital processing sync separator circuits may readily be tailored to operate on the wide variety of sync signals available. However, many types of equipment, such as monitors and projection receivers use analog processing and the present invention is intended for use therein.
The recently adopted SMPTE (Society of Motion Picture and Television Engineers) standards for HDTV horizontal syncs in tri level form (-300 millivolts, +300 millivolts and 0 volts on all colors in a 1 volt analog RGB signal format). The positive and negative portions of the horizontal sync are of very short duration, on the order of 0.5 microseconds. As such, the timing of the positive portion of the horizontal sync pulse interferes with the normal operation of the analog receiver back-porch video clamp circuit. In order to operate properly, the receiver must use the leading edge of the negative portion of the horizontal sync as a timing reference and ignore the positive portion entirely. Further, the receiver must be capable of operating with computer syncs which provide a negative going sync-on-green pulse and with standard NTSC syncs which have a much longer duration.
Another feature of the HDTV standard signal that creates a problem is the 33 KHz interlaced format vertical sync interval. NTSC and computer signals with composite interlaced sync include a series of double horizontal frequency equalizing pulses that occur for several lines before, during and after the vertical sync pulse. The 2H (twice horizontal frequency) equalizing pulses equalize the energy in the R-C integrator (a low pass filter) portion of the typical analog vertical sync separator circuit. If a composite interlaced sync pulse without 2H equalizing pulses both before and during the vertical sync interval is applied to such a circuit, the amount of energy in the R-C integrator will be slightly different in each of the two fields, resulting in distorted interlaced performance. The distortion results in "pairing" of the lines in the even and odd fields and is not acceptable, especially in high resolution monitors and large screen projection receivers.
The 33 KHz HDTV signal has 2H equalizing pulses only during the vertical sync pulse and not before and poses a problem. Further, there is a form of computer sync, referred to as OR'd composite sync, where the vertical pulse is not serrated by either 1H or 2H pulses.
The present invention is concerned with the solution to the horizontal sync problem and the invention in the above-mentioned copending application is concerned with the solution to the vertical problem. It will be appreciated that both inventions may be used in the same receiver as well as individually.